FPGA Implementation of Low Power and Area Efficient Carry Select Adder

In this paper, we have proposed a modified carry select adder which is known as fastest adders that can perform arithmetic operations in Digital signal processors. Modification in the gate level of the Square root Carry Select Adder (SQRT CSLA) structure results in the reduction of area and power of the CSLA structure which offers a simple and efficient function. Depending upon the Regular SQRT CSLA, we have modified the structure of the adders. The proposed design for 128-bit modified CSLA has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. The experimental result shows that the proposed CSLA structure is better than the regular SQRT CSLA.